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general description the max668/max669 constant-frequency, pulse-width modulating (pwm), current-mode dc-dc controllers are designed for a wide range of dc-dc conversion applica- tions including step-up, sepic, flyback, and isolated- output configurations. power levels of 20w or more can be controlled with conversion efficiencies of over 90%. the 1.8v to 28v input voltage range supports a wide range of battery and ac-powered inputs. an advanced bicmos design features low operating current (220?), adjustable operating frequency (100khz to 500khz), soft-start, and a sync input allowing the max668/ max669 oscillator to be locked to an external clock. dc-dc conversion efficiency is optimized with a low 100mv current-sense voltage as well as with maxim? proprietary idle mode control scheme. the controller operates in pwm mode at medium and heavy loads for lowest noise and optimum efficiency, then pulses only as needed (with reduced inductor current) to reduce oper- ating current and maximize efficiency under light loads. a logic-level shutdown input is also included, reducing supply current to 3.5?. the max669, optimized for low input voltages with a guaranteed start-up voltage of 1.8v, requires boot- strapped operation (ic powered from boosted output). it supports output voltages up to 28v. the max668 oper- ates with inputs as low as 3v and can be connected in either a bootstrapped or non-bootstrapped (ic powered from input supply or other source) configuration. when not bootstrapped, it has no restriction on output voltage. both ics are available in an extremely compact 10-pin ?ax package. features ? 1.8v minimum start-up voltage (max669) ? wide input voltage range (1.8v to 28v) ? tiny 10-pin ?ax package ? current-mode pwm and idle mode operation ? efficiency over 90% ? adjustable 100khz to 500khz oscillator or sync input ? 220? quiescent current ? logic-level shutdown ? soft-start applications cellular telephones telecom hardware lans and network systems pos systems max668/max669 1.8v to 28v input, pwm step-up controllers in ?ax ________________________________________________________________ maxim integrated products 1 19-4778; rev 1; 1/02 part max668 eub max669 eub -40? to +85? -40? to +85? temp range pin-package 10 ?ax 10 ?ax evaluation kit available idle mode is a trademark of maxim integrated products. ordering information typical operating circuit max669 freq cs+ sync/ shdn pgnd fb gnd v cc ext ldo ref v out = 28v v in = 1.8v to 28v 1 2 3 4 5 10 9 8 7 6 sync/shdn v cc ext pgnd ref gnd freq ldo max668 max669 m max top view cs+ fb pin configuration for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max668/max669 1.8v to 28v input, pwm step-up controllers in max 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = ldo = 5v, r osc = 200k , t a = 0c to +85c, unless otherwise noted. typical values are at t a = +25c.) v cc to gnd ..........................................................-0.3v to +30v pgnd to gnd....................................................................0.3v sync/ shdn to gnd .............................................-0.3v to +30v ext, ref to gnd.....................................-0.3v to (v ldo + 0.3v) ldo, freq, fb, cs+ to gnd ................................ -0.3v to +6v ldo output current...........................................-1ma to +20ma ref output current..............................................-1ma to +1ma ldo short circuit to gnd .........................................momentary ref short circuit to gnd ..........................................continuous continuous power dissipation (t a = +70c) 10-pin max (derate 5.6mw/c above +70c) ..........444mw operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering,10sec) ..............................+300c 85 100 115 425 500 575 225 250 275 r osc = 200k 1% oscillator frequency oscillator 1.0 1.1 1.2 rising edge, 1% hysteresis ref undervoltage lockout threshold -2 -10 ref load = 0 to 50? ref load regulation 1.225 1.250 1.275 no load, c ref = 0.22? ref output voltage 2.40 2.50 2.60 sensed at ldo, falling edge, hysteresis = 1%, max668 only undervoltage lockout threshold 2.65 5.50 3v v cc 28v (includes ldo dropout) 4.50 5.00 5.50 ldo output voltage reference and ldo regulators 328 max668 pwm controller input voltage range, v cc 3.5 6 sync/ shdn = gnd, v cc = 28v shutdown supply current (v cc ) 220 350 v fb = 1.30v, v cc = 3v to 28v v cc supply current (note 1) 0.2 1 cs+ forced to gnd cs+ input current 51525 idle mode current-sense threshold 2.7 5.5 input voltage range with v cc tied to ldo 1.225 1.250 1.275 fb threshold 1 20 v fb = 1.30v fb input current 85 100 115 current-limit threshold min typ max conditions parameter khz v mv v v v a a a mv mv na v v v units max669 1.8 28.0 ldo load = to 400 5v v cc 28v (includes ldo dropout) r osc = 500k 1% r osc = 100k 1% 0.013 typically 0.013% per mv on cs+; v cs + range is 0 to 100mv for 0 to full load current. fb threshold load regulation %/mv 0.012 typically 0.012% per % duty factor on ext; ext duty factor for a step-up is: 100% (1 C v in /v out ) fb threshold line regulation %/% reference and ldo regulators oscillator pwm controller
v max668/max669 1.8v to 28v input, pwm step-up controllers in ?ax _______________________________________________________________________________________ 3 70 100 500 sync input frequency range sync/ shdn falling edge to shutdown delay 2 5 ext high or low ext on-resistance 1 ext forced to 2v ext sink/source current 1.5 1.8v < v cc < 3v (max669) a sync/ shdn input high voltage 0.30 1.8v < v cc < 3v (max669) ? sync/ shdn input low voltage 0.5 3.0 sync/ shdn = 5v sync/ shdn input current 1.5 6.5 sync/ shdn = 28v v min typ max conditions parameter ? khz units electrical characteristics (continued) (v cc = ldo = 5v, r osc = 200k , t a = 0? to +85?, unless otherwise noted. typical values are at t a = +25?.) electrical characteristics (v cc = ldo = 5v, r osc = 200k , t a = -40? to +85?, unless otherwise noted.) (note 2) 2.40 2.60 sensed at ldo, falling edge, hysteresis = 1%, max669 only ldo undervoltage lockout threshold 2.65 5.50 3v v cc 28v (includes ldo dropout) 4.50 5.50 5v v cc 28v (includes ldo dropout) ldo output voltage reference and ldo regulators v 328 max668 v pwm controller input voltage range, v cc 6 sync/ shdn = gnd, v cc = 28v shutdown supply current (v cc ) 350 v fb = 1.30v, v cc = 3v to 28v ? v cc supply current (note 1) 1 cs+ forced to gnd ? cs+ input current 327 ? idle mode current-sense threshold 2.7 5.5 mv input voltage range with v cc tied to ldo 1.22 1.28 mv fb threshold 20 v fb = 1.30v na fb input current 85 115 v current-limit threshold min max conditions v parameter v units 86 90 94 r osc = 500k ?% max669 ldo load = to 400 1.8 28 3v < v cc < 28v 3v < v cc < 28v 2.0 0.45 v 200 not tested sync input rise/fall time ns 50 200 minimum sync input low pulse width ns 20 45 minimum sync input-pulse duty cycle % 290 minimum ext pulse width ns 87 90 93 r osc = 200k ?% 86 90 94 r osc = 100k ?% maximum duty cycle % pwm controller reference and ldo regulators
max668/max669 1.8v to 28v input, pwm step-up controllers in max 4 _______________________________________________________________________________________ ns % minimum sync input-pulse duty cycle 45 minimum sync input low pulse width 200 sync input rise/fall time not tested 200 ns electrical characteristics (continued) (v cc = ldo = 5v, r osc = 200k? , t a = -40?c to +85?c, unless otherwise noted.) r osc = 200k ? 1% 87 93 sync input frequency range 100 500 khz 1.8v < v cc < 3v (max669) 0.30 v 1.8v < v cc < 3v (max669) 1.5 v sync/ shdn = 28v 6.5 a ext on-resistance ext high or low 5 ? sync/ shdn input current sync/ shdn = 5v 3.0 note 1: this is the v cc current consumed when active but not switching. does not include gate-drive current. note 2: limits at t a = -40?c are guaranteed by design. 222 278 units parameter conditions min max r osc = 200k ? 1% % maximum duty cycle r osc = 500k ? 1% 86 94 425 575 r osc =100k ? 1% khz oscillator frequency 85 115 r osc = 500k ? 1% r osc = 100k ? 1% 86 94 sync/ shdn input high voltage 3v < v cc < 28v 2.0 sync/ shdn input low voltage 3v < v cc < 28v 0.45 v ref output voltage no load, c ref = 0.22f 1.22 1.28 mv ref load regulation ref load = 0 to 50a -10 v ref undervoltage lockout threshold rising edge, 1% hysteresis 1.0 1.2 oscillator
max668/max669 1.8v to 28v input, pwm step-up controllers in max _______________________________________________________________________________________ 5 50 60 65 70 75 80 85 90 95 1 10 100 1000 10,000 efficiency vs. load current (v out = 5v) max668 toc01 load current (ma) efficiency (%) 55 v in = 3.3v v in = 3.6v v in = 2v v in = 2.7v bootstrapped figure 3 r4 = 200k w 70 1 10,000 1000 10 100 max668 efficiency vs. load current (v out = 12v) 85 75 95 80 90 max668 toc02 load current (ma) efficiency (%) v in = 5v non-bootstrapped figure 4 r4 = 200k w max668 efficiency vs. load current (v out = 24v) max668 toc03 load current (ma) efficiency (%) 70 1 10,000 1000 10 100 85 75 95 80 90 v in = 8v v in = 5v v in = 12v non-bootstrapped figure 4 r4 = 200k w 0 1.5 1.0 0.5 2.0 2.5 3.0 0 400 300 100 200 500 600 700 800 900 1000 max669 minimum start-up voltage vs. load current max668 toc04 load current (ma) minimum start-up voltage (v) v out = 5v v out = 12v bootstrapped figure 2 0 0.5 1.5 2.0 2.5 3.0 3.5 010 5 15202530 shutdown current vs. supply voltage max668 toc07 supply voltage (v) shutdown current ( m a) 1.0 current into v cc pin max668 max669 0 400 200 800 600 1000 1200 01015 5 202530 supply current vs. supply voltage max668 toc05 supply voltage (v) supply current ( m a) max669 max668 current into v cc pin r osc = 500k w 0 500 1000 2000 2500 3000 3500 4000 04 2681012 no-load supply current vs. supply voltage max668 toc06 supply voltage (v) no-load supply current ( m a) 1500 v out = 12v bootstrapped figure 2 r4 = 200k w 150 190 210 170 250 230 270 290 -40 -20 0 20 40 60 80 100 supply current vs. temperature max668 toc08 temperature ( c) supply current ( m a) r osc = 100k w r osc = 200k w r osc = 500k w 0.1 1 10 20 ldo dropout voltage vs. ldo current max668 toc09 ldo current (ma) ldo dropout voltage (mv) 300 0 50 100 150 200 250 v in = 3v v in = 4.5v typical operating characteristics (circuits of figures 2, 3, 4, and 5; t a = +25?; unless otherwise noted.)
max668/max669 1.8v to 28v input, pwm step-up controllers in max 6 _______________________________________________________________________________________ typical operating characteristics (continued) (circuits of figures 2, 3, 4, and 5; t a = +25?c; unless otherwise noted.) 1.240 1.242 1.243 1.241 1.245 1.246 1.244 1.248 1.249 1.247 1.250 -40 -20 0 20 40 60 80 100 reference voltage vs. temperature max668 toc10 temperature ( c) reference voltage (v) v cc = 5v 0 100 150 50 250 300 200 400 450 350 500 0 100 200 300 400 500 switching frequency vs. r osc max668 toc11 r osc (k w ) switching frequency (khz) v cc = 5v 0 100 300 400 500 600 -40 0 -20 20 40 60 80 100 switching frequency vs. temperature max668 toc12 temperature ( c) switching frequency (khz) 200 100k w 165k w 499k w v in = 5v 100 1000 10,000 ext rise/fall time vs. capacitance max668 toc13 capacitance (pf) ext rise/fall time (ns) 60 0 10 20 30 40 50 t r , v cc = 3.3v t f , v cc = 3.3v t r , v cc = 5v t f , v cc = 5v
max668/max669 1.8v to 28v input, pwm step-up controllers in max _______________________________________________________________________________________ 7 exiting shutdown max668 toc14 output voltage 5v/div inductor current 2a/div shutdown voltage 5v/div max668, v in = 5v, v out = 12v, load = 1.0a, r osc = 100k w , low voltage, non-bootstrapped 500 m s/div 0v 0v 0a entering shutdown max668 toc15 output voltage 5v/div shutdown voltage 5v/div max668, v in = 5v, v out = 12v, load = 1.0a, low voltage, non-bootstrapped 200 m s/div 0v 0v heavy-load switching waveform max668 toc16 v out 200mv/div ac-coupled i l 1a/div q1, drain 5v/div max668, v in = 5v, v out = 12v, i load = 1.0a, low voltage, non-bootstrapped 1 m s/div 0v 0a load-transient response max668 toc18 output voltage ac-coupled 100mv/div load current 1a/div max668, v in = 5v, v out = 12v, i load = 0.1a to 1.0a, low voltage, non-bootstrapped 1ms/div light-load switching waveform max668 toc17 v out 100mv/div ac-coupled i l 1a/div q1, drain 5v/div max668, v in = 5v, v out = 12v, i load = 0.1a, low voltage, non-bootstrapped 1 m s/div 0v 0a typical operating characteristics (continued) (circuits of figures 2, 3, 4, and 5; t a = +25?; unless otherwise noted.) line-transient response max668 toc19 input voltage 5v/div 0v output voltage 100mv/div ac-coupled max668, v in = 5v to 8v, v out = 12v, load = 1.0a, high voltage, non-bootstrapped 20ms/div
detailed description the max668/max669 current-mode pwm controllers operate in a wide range of dc-dc conversion applica- tions, including boost, sepic, flyback, and isolated out- put configurations. optimum conversion efficiency is maintained over a wide range of loads by employing both pwm operation and maxim?s proprietary idle mode control to minimize operating current at light loads. other features include shutdown, adjustable internal operating frequency or synchronization to an external clock, soft start, adjustable current limit, and a wide (1.8v to 28v) input range. max668 vs. max669 differences differences between the max668 and max669 relate to their use in bootstrapped or non-bootstrapped cir- cuits (table 1). the max668 operates with inputs as low as 3v and can be connected in either a boot- strapped or non-bootstrapped (ic powered from input supply or other source) configuration. when not boot- strapped, the max668 has no restriction on output volt- age. when bootstrapped, the output cannot exceed 28v. the max669 is optimized for low input voltages (down to 1.8v) and requires bootstrapped operation (ic pow- ered from v out ) with output voltages no greater than 28v. bootstrapping is required because the max669 does not have undervoltage lockout, but instead drives ext with an open-loop, 50% duty-cycle start-up oscilla- tor when ldo is below 2.5v. it switches to closed-loop operation only when ldo exceeds 2.5v. if a non-boot- strapped connection is used with the max669 and if v cc (the input voltage) remains below 2.7v, the output voltage will soar above the regulation point. table 2 recommends the appropriate device for each biasing option. max668/max669 1.8v to 28v input, pwm step-up controllers in max 8 _______________________________________________________________________________________ name function 1 ldo 5v on-chip regulator output. this regulator powers all internal circuitry including the ext gate driver. bypass ldo to gnd with a 1f or greater ceramic capacitor. 2 freq oscillator frequency set input. a resistor from freq to gnd sets the oscillator from 100khz (r osc = 500k ? ) to 500khz (r osc = 100k ? ). f osc = 5 x 10 10 / r osc . r osc is still required if an external clock is used at sync/ shdn (see the sync/shdn and freq inputs section). pin 3 gnd analog ground 7 pgnd power ground for ext gate driver and negative current-sense input 6 cs+ positive current-sense input. connect a current-sense resistor, r cs , between cs+ and pgnd. 5 fb feedback input. the fb threshold is 1.25v. 4 ref 1.25v reference output. ref can source 50a. bypass to gnd with a 0.22f ceramic capacitor. 10 sync/ shdn shutdown control and synchronization input. there are three operating modes: sync/ shdn low: dc-dc off. sync/ shdn high: dc-dc on with oscillator frequency set at freq by r osc . sync/ shdn clocked: dc-dc on with operating frequency set by sync clock input. dc-dc conversion cycles initiate on rising edge of input clock. 9 v cc input supply to on-chip ldo regulator. v cc accepts inputs up to 28v. bypass to gnd with a 0.1f ceramic capacitor. 8 ext external mosfet gate-driver output. ext swings from ldo to pgnd. pin description table 1. max668/max669 comparison max668 max669 v cc input range 3v to 28v 1.8v to 28v operation bootstrapped or nonboot- strapped. v cc can be con- nected to input, output, or other voltage source such as a logic supply. must be boot- strapped (v cc must be connect- ed to boosted out- put voltage, v out ). uvlo ic stops switching for ldo below 2.5v. no soft-start yes when ldo is above 2.5v feature
pwm controller the heart of the max668/max669 current-mode pwm controller is a bicmos multi-input comparator that simultaneously processes the output-error signal, the current-sense signal, and a slope-compensation ramp (figure 1). the main pwm comparator is direct sum- ming, lacking a traditional error amplifier and its associ- ated phase shift. the direct summing configuration approaches ideal cycle-by-cycle control over the output voltage since there is no conventional error amp in the feedback path. in pwm mode, the controller uses fixed-frequency, cur- rent-mode operation where the duty ratio is set by the input/output voltage ratio (duty ratio = (v out - v in ) / v in in the boost configuration). the current-mode feedback loop regulates peak inductor current as a function of the output error signal. at light loads the controller enters idle mode. during idle mode, switching pulses are provided only as need- ed to service the load, and operating current is mini- mized to provide best light-load efficiency. the minimum-current comparator threshold is 15mv, or 15% of the full-load value (i max ) of 100mv. when the con- troller is synchronized to an external clock, idle mode occurs only at very light loads. bootstrapped/non-bootstrapped operation low-dropout regulator (ldo) several ic biasing options, including bootstrapped and non-bootstrapped operation, are made possible by an on-chip, low-dropout 5v regulator. the regulator input is at v cc , while its output is at ldo. all max668/max669 functions, including ext, are internally powered from ldo. the v cc -to-ldo dropout voltage is typically 200mv (300mv max at 12ma), so that when v cc is less than 5.2v, ldo is typically v cc - 200mv. when ldo is in dropout, the max668/max669 still operate with v cc as low as 3v (as long as ldo exceeds 2.7v), but with reduced amplitude fet drive at ext. the maximum v cc input voltage is 28v. ldo can supply up to 12ma to power the ic, supply gate charge through ext to the external fet, and sup- ply small external loads. when driving particularly large fets at high switching rates, little or no ldo current may be available for external loads. for example, when switched at 500khz, a large fet with 20nc gate charge requires 20nc x 500khz, or 10ma. v cc and ldo allow a variety of biasing connections to optimize efficiency, circuit quiescent current, and full- load start-up behavior for different input and output voltage ranges. connections are shown in figures 2, 3, 4, and 5. the characteristics of each are outlined in table 1. max668/max669 1.8v to 28v input, pwm step-up controllers in max _______________________________________________________________________________________ 9 antisat mux low-voltage start-up oscillator (max669 only) +a -a x6 +c -c x1 +s -s x1 slope compensation sq bias osc osc freq sync/shdn 0 1 ldo pgnd 1.25v ref ext uvlo v cc r1 552k r2 276k r3 276k 100mv 15mv i max i min main pwm comparator 1.25v fb current sense cs+ max668 max669 ldo max669 only r figure 1. max668/max669 functional diagram
max668/max669 1.8v to 28v input, pwm step-up controllers in max 10 ______________________________________________________________________________________ max669 ldo cs+ ref freq v cc sync/ shdn pgnd fb gnd n1 ext v in = 1.8v to 12v c3 0.22 m f c2 0.1 m f c4 1 m f r4 100k 1% r1 0.02 w r2 218k 1% r3 24.9k 1% c7 220pf d1 mbrs340t3 c5 68 m f 20v c6 68 m f 20v c8 0.1 m f 3 5 7 6 8 2 4 9 1 10 v out = 12v @ 0.5a c1 68 m f 20v l1 4.7 m h irf7401 figure 2. max669 high-voltage bootstrapped configuration max669 ldo cs+ ref freq v cc sync/ shdn pgnd fb gnd n1 ext v in = 1.8v to 5v c3 0.22 m f c2 1 m f r4 100k 1% r1 0.02 w r2 75k 1% r3 24.9k 1% c7 220pf d1 mbrs340t3 c4 68 m f 10v c5 68 m f 10v c6 0.1 m f 3 5 7 6 8 2 4 9 1 10 v out = 5v @ 1a c1 68 m f 10v l1 4.7 m h fds6680 irf7401 figure 3. max669 low-voltage bootstrapped configuration bootstrapped operation with bootstrapped operation, the ic is powered from the circuit output (v out ). this improves efficiency when the input voltage is low, since ext drives the fet with a higher gate voltage than would be available from the low-voltage input. higher gate voltage reduces the fet on-resistance, increasing efficiency. other (unde- sirable) characteristics of bootstrapped operation are increased ic operating power (since it has a higher operating voltage) and reduced ability to start up with high load current at low input voltages. if the input volt- age range extends below 2.7v, then bootstrapped operation with the max669 is the only option. with v cc connected to v out , as in figure 2, ext volt- age swing is 5v when v cc is 5.2v or more, and v cc - 0.2v when v cc is less than 5.2v. if the output voltage does not exceed 5.5v, the on-chip regulator can be disabled by connecting v cc to ldo (figure 3). this eliminates the ldo forward drop and supplies maxi- mum gate drive to the external fet.
non-bootstrapped operation with non-bootstrapped operation, the ic is powered from the input voltage (v in ) or another source, such as a logic supply. non-bootstrapped operation (figure 4) is recommended (but not required) for input voltages above 5v, since the ext amplitude (limited to 5v by ldo) at this voltage range is no higher than it would be with bootstrapped operation. note that non-boot- strapped operation is required if the output voltage exceeds 28v, since this level is too high to safely con- nect to v cc . also note that only the max668 can be used with non-bootstrapped operation . if the input voltage does not exceed 5.5v, the on-chip regulator can be disabled by connecting v cc to ldo (figure 5). this eliminates the regulator forward drop and supplies the maximum gate drive to the external fet for lowest on-resistance. disabling the regulator also reduces the non-bootstrapped minimum input volt- age from 3v to 2.7v. max668/max669 1.8v to 28v input, pwm step-up controllers in max ______________________________________________________________________________________ 11 max668 ldo cs+ ref freq v cc sync / shdn pgnd fb gnd n1 ext v in = 2.7v to 5.5v c3 0.22 m f c2 1 m f r4 100k 1% r1 0.02 w r2 218k 1% r3 24.9k 1% c7 220pf d1 mbrs340t3 c4 68 m f 20v c5 68 m f 20v c6 0.1 m f 3 5 7 6 8 2 4 9 1 10 v out = 12v @ 1a c1 68 m f 10v l1 4.7 m h fds6680 figure 5. max668 low-voltage non-bootstrapped configuration max668 ldo cs+ ref freq v cc pgnd fb gnd n1 ext v in = 3v to 12v c3 0.22 m f c4 1 m f c2 0.1 m f r4 100k 1% r1 0.02 w r2 218k 1% r3 24.9k 1% c7 220pf d1 mbrs340t3 c5 68 m f 20v c6 68 m f 20v c8 0.1 m f 3 5 7 6 8 2 4 9 1 10 v out = 12v @ 1a c1 68 m f 20v l1 4.7 m h fds6680 sync/ shdn figure 4. max668 high-voltage non-bootstrapped configuration
max668/max669 1.8v to 28v input, pwm step-up controllers in max 12 ______________________________________________________________________________________ table 2. bootstrapped and non-bootstrapped configurations configuration figure use with: input voltage range* (v) output voltage range (v) comments high-voltage, bootstrapped figure 2 max669 1.8 to 28 3v to 28 connect v cc to v out . provides maximum external fet gate drive for low-voltage (input <3v) to high- voltage (output >5.5v) boost circuits. v out cannot exceed 28v. low-voltage, bootstrapped figure 3 max669 1.8 to 5.5 2.7 to 5.5 connect v out to v cc and ldo . provides maxi- mum possible external fet gate drive for low-volt- age designs, but limits v out to 5.5v or less. high-voltage, non-bootstrapped figure 4 max668 3 to 28 v in to connect v in to v cc . provides widest input and out- put range, but external fet gate drive is reduced for v in below 5v. low-voltage, non-bootstrapped figure 5 max668 2.7 to 5.5 v in to connect v in to v cc and ldo . fet gate-drive amplitude = v in for logic-supply (input 3v to 5.5v) to high-voltage (output >5.5v) boost circuits. ic oper- ating power is less than in figure 4, since ic current does not pass through the ldo regulator. extra ic supply, non-bootstrapped none max668 not restricted v in to connect v cc and ldo to a separate supply (v bias ) that powers only the ic . fet gate-drive amplitude = v bias . input power source (v in) and output voltage range (v out ) are not restricted, except that v out must exceed v in . in addition to the configurations shown in table 2, the following guidelines may help when selecting a config- uration: 1) if v in is ever below 2.7v, v cc must be boot- strapped to v out and the max669 must be used. if v out never exceeds 5.5v, ldo may be shorted to v cc and v out to eliminate the dropout voltage of the ldo regulator. 2) if v in is greater than 3v, v cc can be powered from v in , rather than from v out (non-bootstrapped). this can save quiescent power consumption, espe- cially when v out is large. if v in never exceeds 5.5v, ldo may be shorted to v cc and v in to elimi- nate the dropout voltage of the ldo regulator. 3) if v in is in the 3v to 4.5v range (i.e., 1-cell li+ or 3-cell nimh battery range), bootstrapping v cc from v out , although not required, may increase overall efficiency by increasing gate drive (and reducing fet resistance) at the expense of quiescent power consumption. 4) if v in always exceeds 4.5v, v cc should be tied to v in , since bootstrapping from v out does not increase gate drive from ext but does increase quiescent power dissipation. * for standard step-up dc-dc circuits (as in figures 2, 3, 4, and 5), regulation cannot be maintained if v in exceeds v out . sepic and transformer-based circuits do not have this limitation.
sync/ shdn and freq inputs the sync/ shdn pin provides both external-clock syn- chronization (if desired) and shutdown control. when sync/ shdn is low, all ic functions are shut down. a logic high at sync/ shdn selects operation at a fre- quency set by r osc , connected from freq to gnd. the relationship between f osc and r osc is: r osc = 5 x 10 10 / f osc so a 500khz operating frequency, for example, is set with r osc = 100k . rising clock edges on sync/ shdn are interpreted as synchronization inputs. if the sync signal is lost while sync/ shdn is high, the internal oscillator takes over at the end of the last cycle and the frequency is returned to the rate set by r osc . if sync is lost with sync/ shdn low, the ic waits for 70s before shutting down. this maintains output regulation even with intermittent sync signals. when an external sync signal is used, idle mode switchover at the 15mv current-sense threshold is disabled so that idle mode only occurs at very light loads. also, r osc should be set for a frequency 15% below the sync clock rate: r osc(sync) = 5 x 10 10 / (0.85 x f sync ) soft-start the max668/max669 feature a digital soft start which is preset and requires no external capacitor. upon start-up, the peak inductor increments from 1/5 of the value set by r cs , to the full current-limit value, in five steps over 1024 cycles of f osc or f sync . for example, with an f osc of 200khz, the complete soft-start sequence takes 5ms. see the typical operating characteristics for a photo of soft-start operation. soft- start is implemented: 1) when power is first applied to the ic, 2) when exiting shutdown with power already applied, and 3) when exiting undervoltage lockout. the max669s soft-start sequence does not start until ldo reaches 2.5v. design procedure the max668/max669 can operate in a number of dc- dc converter configurations including step-up, sepic (single-ended primary inductance converter), and fly- back. the following design discussions are limited to step-up, although sepic and flyback examples are shown in the application circuits section. setting the operating frequency the max668/max669 can be set to operate from 100khz to 500khz. choice of operating frequency will depend on number of factors: 1) noise considerations may dictate setting (or syn- chronizing) f osc above or below a certain frequency or band of frequencies, particularly in rf applica- tions. 2) higher frequencies allow the use of smaller value (hence smaller size) inductors and capacitors. 3) higher frequencies consume more operating power both to operate the ic and to charge and discharge the gate of the external fet. this tends to reduce efficiency at light loads; however, the max668/ max669s idle mode feature substantially increases light-load efficiency. 4) higher frequencies may exhibit poorer overall effi- ciency due to more transition losses in the fet; however, this shortcoming can often be nullified by trading some of the inductor and capacitor size benefits for lower-resistance components. the oscillator frequency is set by a resistor, r osc , con- nected from freq to gnd. r osc must be connected whether or not the part is externally synchronized r osc is in each case: r osc = 5 x 10 10 / f osc when not using an external clock. r osc(sync) = 5 x 10 10 / (0.85 x f sync ) when using an external clock, f sync . setting the output voltage the output voltage is set by two external resistors (r2 and r3, figures 2, 3, 4, and 5). first select a value for r3 in the 10k to 1m range. r2 is then given by: r2 = r3 [(v out / v ref ) C 1] where v ref is 1.25v. determining inductance value for most max668/max669 boost designs, the inductor value (l ideal ) can be derived from the following equa- tion, which picks the optimum value for stability based on the max668/max669s internally set slope compen- sation: l ideal = v out / (4 x i out x f osc ) the max668/max669 allow significant latitude in induc- tor selection if l ideal is not a convenient value. this may happen if l ideal is a not a standard inductance (such as 10h, 22h, etc.), or if l ideal is too large to be obtained with suitable resistance and saturation-cur- rent rating in the desired size. inductance values small- er than l ideal may be used with no adverse stability effects; however, the peak-to-peak inductor current (i lpp ) will rise as l is reduced. this has the effect of raising the required i lpk for a given output power and also requiring larger output capacitance to maintain a max668/max669 1.8v to 28v input, pwm step-up controllers in max ______________________________________________________________________________________ 13
max668/max669 given output ripple. an inductance value larger than l ideal may also be used, but output-filter capacitance must be increased by the same proportion that l has to l ideal . see the capacitor selection section for more information on determining output filter values. due the max668/max669?s high switching frequencies, inductors with a ferrite core or equivalent are recom- mended. powdered iron cores are not recommended due to their high losses at frequencies over 50khz. determining peak inductor current the peak inductor current required for a particular out- put is: i lpeak = i ldc + (i lpp / 2) where i ldc is the average dc input current and i lpp is the inductor peak-to-peak ripple current. the i ldc and i lpp terms are determined as follows: where v d is the forward voltage drop across the schottky rectifier diode (d1), and v sw is the drop across the external fet, when on. where l is the inductor value. the saturation rating of the selected inductor should meet or exceed the calcu- lated value for i lpeak , although most coil types can be operated up to 20% over their saturation rating without difficulty. in addition to the saturation criteria, the induc- tor should have as low a series resistance as possible. for continuous inductor current, the power loss in the inductor resistance, p lr , is approximated by: p lr @ (i out x v out / v in ) 2 x r l where r l is the inductor series resistance. once the peak inductor current is selected, the current- sense resistor (r cs ) is determined by: r cs = 85mv / i lpeak for high peak inductor currents (>1a), kelvin sensing connections should be used to connect cs+ and pgnd to r cs . pgnd and gnd should be tied together at the ground side of r cs . power mosfet selection the max668/max669 drive a wide variety of n-channel power mosfets (nfets). since ldo limits the ext output gate drive to no more than 5v, a logic-level nfet is required. best performance, especially at low input voltages (below 5v), is achieved with low-thresh- old nfets that specify on-resistance with a gate- source voltage (v gs ) of 2.7v or less. when selecting an nfet, key parameters can include: 1) total gate charge (q g ) 2) reverse transfer capacitance or charge (c rss ) 3) on-resistance (r ds(on) ) 4) maximum drain-to-source voltage (v ds(max) ) 5) minimum threshold voltage (v th(min) ) at high switching rates, dynamic characteristics (para- meters 1 and 2 above) that predict switching losses may have more impact on efficiency than r ds(on), which predicts dc losses. q g includes all capacitances associated with charging the gate. in addition, this parameter helps predict the current needed to drive the gate at the selected operating frequency. the continu- ous ldo current for the fet gate is: i gate = q g x f osc for example, the mmft3055l has a typical q g of 7nc (at v gs = 5v); therefore, the i gate current at 500khz is 3.5ma. use the fet manufacturer?s typical value for q g in the above equation, since a maximum value (if sup- plied) is usually too conservative to be of use in esti- mating i gate . diode selection the max668/max669?s high switching frequency demands a high-speed rectifier. schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. ensure that the diode?s average current rating is adequate using the diode manufacturer?s data, or approximate it with the following formula: also, the diode reverse breakdown voltage must exceed v out . for high output voltages (50v or above), schottky diodes may not be practical because of this voltage requirement. in these cases, use a high-speed silicon rectifier with adequate reverse voltage. capacitor selection output filter capacitor the minimum output filter capacitance that ensures sta- bility is: where v in(min) is the minimum expected input voltage. typically c out(min) , though sufficient for stability, will c (7.5v x l / l ) (2 r x v x f ) out(min) ideal cs in(min) osc = p ii i- i 3 diode out lpeak out =+ 1.8v to 28v input, pwm step-up controllers in max 14 ______________________________________________________________________________________ i = i (v + v (v v ldc out out d in sw ) ) i = (v v ) (v + v v ) l x f (v + v ) lpp in sw out d in osc out d
not be adequate for low output voltage ripple. since output ripple in boost dc-dc designs is dominated by capacitor equivalent series resistance (esr), a capaci- tance value 2 or 3 times larger than c out(min) is typi- cally needed. low-esr types must be used. output ripple due to esr is: v ripple(esr) = i lpeak x esr cout input capacitor the input capacitor (c in ) in boost designs reduces the current peaks drawn from the input supply and reduces noise injection. the value of c in is largely determined by the source impedance of the input supply. high source impedance requires high input capacitance, particularly as the input voltage falls. since step-up dc- dc converters act as constant-power loads to their input supply, input current rises as input voltage falls. consequently, in low-input-voltage designs, increasing c in and/or lowering its esr can add as many as five percentage points to conversion efficiency. a good starting point is to use the same capacitance value for c in as for c out . bypass capacitors in addition to c in and c out , three ceramic bypass capacitors are also required with the max668/max669. bypass ref to gnd with 0.22f or more. bypass ldo to gnd with 1f or more. and bypass v cc to gnd with 0.1f or more. all bypass capacitors should be located as close to their respective pins as possible. compensation capacitor output ripple voltage due to c out esr affects loop stability by introducing a left half-plane zero. a small capacitor connected from fb to gnd forms a pole with the feedback resistance that cancels the esr zero. the optimum compensation value is: where r2 and r3 are the feedback resistors (figures 2, 3, 4, and 5). if the calculated value for c fb results in a non-standard capacitance value, values from 0.5c fb to 1.5c fb will also provide sufficient compensation. applications information starting under load in non-bootstrapped configurations (figures 4 and 5), the max668 can start up with any combination of out- put load and input voltage at which it can operate when already started. in other words, there are no special limitations to start-up in non-bootstrapped circuits. in bootstrapped configurations with the max668 or max669, there may be circumstances where full load current can only be applied after the circuit has started and the output is near its set value. as the input voltage drops, this limitation becomes more severe. this char- acteristic of all bootstrapped designs occurs when the mosfet gate is not fully driven until the output voltage rises. this is problematic because a heavily loaded out- put cannot rise until the mosfet has low on-resis- tance. in such situations, low-threshold fets (v th < v in(min) ) are the most effective solution. the typical operating characteristics section shows plots of start- up voltage versus load current for a typical boot- strapped design. layout considerations due to high current levels and fast switching waveforms that radiate noise, proper pc board layout is essential. protect sensitive analog grounds by using a star ground configuration. minimize ground noise by connecting gnd, pgnd, the input bypass-capacitor ground lead, and the output-filter ground lead to a single point (star ground configuration). also, minimize trace lengths to reduce stray capacitance, trace resistance, and radiat- ed noise. the trace between the external gain-setting resistors and the fb pin must be extremely short, as must the trace between gnd and pgnd. application circuits low-voltage boost circuit figure 3 shows the max669 operating in a low-voltage boost application. the max669 is configured in the bootstrapped mode to improve low input voltage per- formance. the irf7401 n-channel mosfet was select- ed for q1 in this application because of its very low 0.7v gate threshold voltage (v gs ). this circuit provides a 5v output at greater than 2a of output current and operates with input voltages as low as 1.8v. efficiency is typically in the 85% to 90% range. 12v boost application figure 5 shows the max668 operating in a 5v to 12v boost application. this circuit provides output currents of greater than 1a at a typical efficiency of 92%. the max668 is operated in non-bootstrapped mode to mini- mize the input supply current. this achieves maximum light-load efficiency. if input voltages below 5v are used, the ic should be operated in bootstrapped mode to achieve best low-voltage performance. 4-cell to 5v sepic power supply figure 6 shows the max668 in a sepic (single-ended primary inductance converter) configuration. this con- figuration is useful when the input voltage can be either max668/max669 1.8v to 28v input, pwm step-up controllers in max ______________________________________________________________________________________ 15 c c x esr (r2 x r3) / (r2 + r3) fb out cout =
max668/max669 larger or smaller than the output voltage, such as when converting four nimh, nicd, or alkaline cells to a 5v output. the sepic configuration is often a good choice for combined step-up/step-down applications. the n-channel mosfet (q1) must be selected to with- stand a drain-to-source voltage (v ds ) greater than the sum of the input and output voltages. the coupling capacitor (c2) must be a low-esr type to achieve max- imum efficiency. c2 must also be able to handle high ripple currents; ordinary tantalum capacitors should not be used for high-current designs. the circuit in figure 6 provides greater than 1a output current at 5v when operating with an input voltage from 3v to 25v. efficiency will typically be between 70% and 85%, depending upon the input voltage and output cur- rent. isolated 5v to 5v power supply the circuit of figure 7 provides a 5v isolated output at 400ma from a 5v input power supply. transformer t1 provides electrical isolation for the forward path of the converter, while the tlv431 shunt regulator and moc211 opto-isolator provide an isolated feedback error voltage for the converter. the output voltage is set by resistors r2 and r3 such that the mid-point of the divider is 1.24v (threshold of tlv431). output voltage can be adjusted from 1.24v to 6v by selecting the proper ratio for r2 and r3. for output voltages greater than 6v, substitute the tl431 for the tlv431, and use 2.5v as the voltage at the midpoint of the voltage- divider. 1.8v to 28v input, pwm step-up controllers in max 16 ______________________________________________________________________________________ r3 100k r4 0.02w r1 75k r2 25k c4 520pf v in 3v to 25v 30v fds6680 q1 l1 ctx5-4 max668 shdn v cc 910 ldo freq d1: mbr5340t3, 3a, 40v schottky diode r4: wsl-2512-r020f, 0.02 w c3: avx tpsz686m020r0150, 68 mf, 150mw esr ref ext cs+ 8 6 pgnd gnd 7 3 fb 1 2 4 5 1mf 22mf x 3 @ 35v c3 68mf x 3 v out 5v @ 1a 4.9mh c2 10mf @ 35v d1 40v 0.22mf figure 6. max668 in sepic configuration chip information transistor count: 1861
max668/max669 1.8v to 28v input, pwm step-up controllers in max ______________________________________________________________________________________ 17 max668 ldo cs+ fb shdn pgnd freq ref v cc gnd t1 1:2 ext v in = +5v t1: coiltronics ctx03-14232 5v @ 400ma 5v return 0.1 w r2 301kw 1% 510 w tlv431 610 w 0.068 m f r3 100kw 1% mbr0540l mbr0540l 47 m h 220 m f 10v 0.22 m f 1 m f 100k 10k moc211 irf7603 220 m f 10v 0.1 m f figure 7. isolated 5v to 5v at 400ma power supply
max668/max669 package infor mation 1.8v to 28v input, pwm step-up contr ollers in max 10lumaxb.eps (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products.

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